In an image processor for decoding a variable-length coded string such as an MPEG stream, there recently is increasing necessity for decoding an HD (high definition) image including a large number of pixels and the like, and it is necessary to increase the speed of the decoding processing.
FIG. 4 is an explanatory diagram of processing performed in a conventional image processor. FIG. 4A is a diagram for explaining a processing unit of an image. For example, in an HD image, one screen includes 1920×1080 pixels, and in a standard image, one screen includes 720×480 pixels. Such a screen is processed in a unit of 16×16 pixels designated as a macroblock. A macroblock is divided, for processing, into six blocks each including 8×8 pixel data, namely, four luminance blocks Y0, Y1, Y2 and Y3 and two chrominance blocks Cb and Cr.
FIG. 4B is a diagram for explaining a bit stream of variable-length coded image data. Data corresponding to every macroblock are transferred in the order of a header, the luminance blocks Y0 through Y3 and the chrominance blocks Cb and Cr.
FIG. 4C is a diagram for explaining pipeline processing performed in the conventional image processor. In the decoding processing, the pipeline processing is generally carried out in units of blocks each including 8×8 pixels for increasing the speed of the processing. Specifically, for example, a unit A for carrying out variable-length decoding, inverse quantization and inverse scanning, a unit B for carrying out inverse discrete cosine transform and a unit C for carrying out motion compensation are operated in parallel as shown in FIG. 4C.
In conducting such pipeline processing, the processing of the respective units are preferably ended in an average number of clock cycles. In the unit A, however, all the sixty-four values of every block are subjected to the inverse quantization and the inverse scanning so as to store resultant data, and hence, the number of clock cycles necessary for processing one block is larger than in the other units.
FIG. 5 is a block diagram of the conventional image processor. The image processor of FIG. 5 includes a variable-length decoding part 81, an inverse quantization/inverse scanning part 82 and a data storage part 83 as the unit A, a data reading part 84 and an inverse discrete cosine transform part 85 as the unit B and a motion compensation part 86 as the unit C.
In FIG. 5, the variable-length decoding part 81 variable-length decodes an input bit stream, and converts data of every block into a string of sixty-four values to be successively output to the inverse quantization/inverse scanning part 82. The inverse quantization/inverse scanning part 82 carries out the inverse quantization and the inverse scanning on all the sixty-four values of every block output from the variable/length decoding part 81, so as to store all the resultant DCT coefficients in the data storage part 83.
The data reading part 84 reads the DCT coefficients from the data storage part 83 and outputs them to the inverse discrete cosine transform part 85. The inverse discrete cosine transform part 85 carries out the inverse discrete cosine transform on the DCT coefficients and outputs obtained decoded image data to the motion compensation part 86. The motion compensation part 86 carries out the motion compensation by using the reconstructed image data.
Among DCT (discrete cosine transform) coefficients obtained through variable-length decoding of image data such as an MPEG stream, the proportion of those having a value of 0 is high except for those obtained from a special image. In the conventional image processor as shown in FIG. 5, all the coefficients obtained through the variable-length decoding processing are subjected to the inverse quantization and the inverse scanning so as to store resultant data, which is a bottleneck in increasing the speed of the decoding processing. Also, when such decoding processing is executed on hardware, it is preferred that the processing is realized in a circuit of which area is as small as possible.